The present invention relates to a horizontal insulated-gate bipolar transistor (hereinafter called "IGBT") suitable for, for example, being incorporated in an integrated circuit device, and a process of producing the same.
As is well known, IGBTs feature high input impedance retained by insulated gates and low output impedance by bipolar transistors in combination, and have become widely employed as high-voltage, large-current transistors for uses in which extremely high frequency characteristics are not particularly required. Heretofore, IGBTs have normally been utilized in the form of separate elements of vertical structure, but with the trend for power devices to be made with so-called intelligence, there are increased demands for fabricating a plurality of IGBTs together with relevant control circuits into one integrated circuit device. Since the planar structure is advantageous for integration, horizontal IGBTs are often employed.
The simplest way of fabricating a horizontal IGBT is to relocate the rear structure of a conventional chip of vertical structure onto its surface side. FIG. 1 is a sectional view showing a unit structure of a typical conventional horizontal IGBT. A chip or wafer for an integrated circuit is usually prepared by, for example, growing an n-type epitaxial layer 2 on a p-type semiconductor substrate 1 and the horizontal IGBT is made by repeatedly fabricating the unit structure U on both left and right sides with the epitaxial layer 2 as a semiconductor region for the IGBT.
The central portion of FIG. 1 is similar to that of vertical structure. A p-type base layer 3 and a base contact layer 4 with a high impurity concentration are diffused from the surface of an n-type semiconductor region 2 and a polycrystalline silicon gate 5 is disposed via a gate oxide film 5a on both peripheral edge portions of the base layer 3. Simultaneously, an n-type source layer 6 with a high impurity concentration is diffused to be buried under the insulated gate 5 as shown in FIG. 1. Then aluminum electrode films 9 are used to short the p-type base contact layer 4 and the n-type source layer 6 so as to form an emitter terminal E, and further a gate terminal G is connected to the insulated gate 5.
The left and right end portions of FIG. 1 correspond to the rear structure of a vertical structure chip. In this case, an n-type buffer layer 7 with relatively high impurity concentration is diffused from the surface of the semiconductor region 2 and a p-type collector layer 8 with high impurity concentration is diffused inside the former and further electrode films 9 are conductively connected to the surface of the latter to provide a collector terminal C. The collector layer 8 is normally fabricated by simultaneous diffusion as the p-type base contact layer 4 with high impurity concentration.
In the case of the horizontal IGBT of FIG. 1, a positive voltage with respect to the emitter terminal E is applied to the gate terminal G while a voltage is being applied across the emitter and collector terminals E and C. Then an n-type channel is formed on the surface of the p-type base layer 3 beneath the insulated gate 5 and electrons as majority carriers flow from the n-type source layer 6 via the semiconductor region 2 and the buffer layer 7 to the collector layer 8. When holes as minority carriers are reversely injected from the collector layer 8 via the buffer layer 7 into the semiconductor region 2, a bipolar transistor comprising the p-type base layer 3, the n-type semiconductor region 2 and the collector layer 8 is turned on with a base current of the holes, and due to the so-called conductivity modulation action originating from the electrons and holes in the semiconductor region 2, the main terminal E conducts to the main terminal C at an extremely low on-voltage. When the IGBT is turn off, the electrons flowing through the channel beneath the insulated gate 5 are cut off by applying a voltage equal to or more negative than that at the emitter terminal E to the gate terminal G. The buffer layer 7 is used for controlling the hole injection quantity from the collector layer 8 to the semiconductor region 2.
The aforesaid horizontal IGBT is rendered capable of withstanding higher voltage by widening the gap between the base layer 3 and the collector layer 8 and capable of passing larger current by increasing the number of unit structures U. Notwithstanding, the horizontal IGBT still poses a serious problem in that latch-up tends to easily occur as compared with the vertical structure. FIG. 2 shows an enlarged right-hand portion of FIG. 1 wherein flow paths of electrons e as majority carriers and holes h as minority carriers are illustrated. The electrons e flow from the source layer 6 through a channel beneath the insulated gate 5 and enter the semiconductor region 2. Then they flow along the surface of the semiconductor region and flow through the buffer layer 7 into the collector layer 8. On the other hand, the holes h are injected from the collector layer 8 via the buffer layer 7 into the semiconductor region 2, and due to the Coulomb's force from the electrons e, the holes pass in a range close to the surface and contribute to the conductivity modulation. Then the holes enter the base layer 3 and flow under the source layer 6 into the base contact layer 4.
As stated above, the holes h as minority carriers laterally flow through the base layer 3 beneath the source layer 6 in the horizontal IGBT, and as the current due to the holes h increases, they are injected into the source layer 6. Thus the pnpn four-layer thyristor structure existing among the p-type collector layer 8, the n-type semiconductor region 2, the p-type base layer 3 and the n-type source layer 6 tends to ignite to cause latch-up. The injection of the holes h into the source layer 6 like this easily occurs especially when an overvoltage is applied across the collector and emitter terminals C and E while the IGBT is in the off state. The reason for this is that when a voltage drop becomes greater due to the holes h laterally flowing through the base layer 3, since the emitter terminal E shorts the base layer 3 and the source layer 6, the potential at the place shown by I in FIG. 2 rises relatively and causes the pn junction at the place to be biased in the forward direction, thus making holes h readily injected. Accordingly, there are problems that an allowable current which is allowed to flow and the latch-up withstanding quantity considerably lower in the case of the horizontal IGBT in comparison with the vertical structure.